Important characteristics of mass information storage devices of the future should be high speed, low power consumption, low cost and small size. To achieve this aim, magnetic random access memories (MRAMs) have been proposed due to their non-volatile nature. Unlike dynamic random access memory (DRAM) cells, non-volatile memory cells such as MRAM cells do not require a complex circuitry for perpetual electronic refreshing of the information stored, and thus can in principle outperform DRAM cells in all above mentioned characteristics.
The first of such MRAMs were based on magnetic multi-layer structures, deposited on a substrate. U.S. Pat. No. 5,343,422, for example, discloses a structure in which two layers of ferromagnetic material are separated by a layer of non-magnetic metallic conducting material. One of the magnetic materials, called the ferromagnetic fixed layer (FMF), has a fixed direction of magnetic moment, e.g. by having a particularly high coercive field or strong uni-axial anisotropy. The magnetisation of the other magnetic layer, called the ferromagnetic soft layer (FMS), is free to change direction between parallel and anti-parallel alignment relative to the direction of the magnetic moment of FMF.
The state of the storage element represents a logical “1” or “0” depending on whether the directions of the magnetic moments of the magnetic layers are aligned parallel or anti-parallel, respectively. Because the resistance levels are different for different mutual orientations of the magnetic layers, the structure acts as a spin valve. It thus allows the sensing of the state of the storage element by measuring the differential resistance ΔR/R with a current, where ΔR is the difference in resistance of the storage element for two different states of orientation, and R is its total resistance. Due to the high conductance of the device, strong currents are needed to obtain a high enough output voltage signal level for the sensing operation. A switching between these orientations can be achieved by passing write currents in the vicinity of the FMS, usually by using write lines which run past the layered structure on either side. These write currents, which do not pass through the layered structure itself, induce a magnetic field at the location of the FMS which alters the orientation of the FMS, if it is stronger than the coercive field Hc of the FMS.
The main disadvantage of this set-up is the relatively high power consumption during both write and sense operations due to the high conductance of the structure. For example, conducting thin films have low sheet resistivities of about 10Ω/μm2 leading to cell resistances of about 10Ω for currently realisable devices. Such devices require high sense currents of the order of a 0.1 mA in order to get voltage signals in the region of 1 mV. Therefore MRAM storage devices with higher resistance have been sought for.
An alternative was proposed by J. M. Doughton, J. Appl. Phys., 81, pp. 3758-3763 (1997). There, the conducting non-magnetic spacer layer between the two magnetic layers is replaced by an insulator. The device therefore forms a magnetic tunnel junction (MTJ), where spin polarised electrons tunnel through the insulator. It has a high impedance with resistivity values of 104-109Ω/μm2, allowing for high speed MRAMs. Further, when put into a two dimensional array such an MRAM cell can be controlled by just using two lines per cell, the minimum needed to locate the cell in such an array. Such an array, shown in FIG. 1A is proposed in U.S. Pat. No. 5,640,343, the disclosure of which is incorporated herein by reference.
With reference to FIG. 1A, the memory cell elements are arranged vertically between parallel electrically conductive word lines 1, 2, 3 and bit lines 4, 5, 6. This makes the device topologically simple and allows in principle for a denser array than is achievable with a similar line-width process for DRAMs. The MRAM array shown in FIG. 1A uses memory cells 9, shown in FIG. 1B, that comprise each a MTJ 8 and a p-n diode 7 in electrical series connection. The diode 7 is formed as a silicon junction with an n-type layer 10 and a p-type layer 11. It is connected by an intermediate layer 12 to the MTJ 8, which is formed as a series of stacked layers comprising a template layer 15, a first ferromagnetic layer 16, a anti-ferromagnetic layer 18 a FMF 20, a tunnelling barrier layer 22, a FMS 24 and contact layer 25. The presence of the diode 7 in the memory cell 9 allows the use of only two lines per cell. The device can be operated such that during a sense operation only one memory cell in the MRAM will be forward biased whereas the remaining cells will either not be biased or reverse biased. Since the reverse bias is always kept below the breakdown voltage of the diode 7, no current flows through these cells.
A cell is written by sending simultaneously a current through the word and bit line crossing at the location of the cell. Although these currents do not pass through the cell itself, the magnetic field induced by the current at the location of the FMS is strong enough to switch the orientation of the magnetic moment between its two preferred states along the easy axis of the FMS. The FMF, however, has a coercivity that is high enough such that its magnetic moment is left unchanged in this process. Similarly, in the other memory cells which lie along either the bit or word line used in the switching, the magnetic field induced by the current passing only in one line is not strong enough to switch the FMS. This set-up however still suffers from high power consumption during write operations.
As a consequence of the magnetic fields of the switching currents the density of planar integration of MJT cells in an array is also limited Further, the supporting electric circuitry has to be designed such that both write and sense currents can be effected to flow along different paths which makes such circuitry quite complex.